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Chipset Features Setup

This page contains useful information about the Chipset Features found on modern motherboards. To avoid clutter on what is a very extensive section, we are concentrating on newer Pentium II motherboard fields.

SDRAM Bank Interleave

This field sets the options to control the type of interleaving used by the system RAM. Interleaving allows one bank to refresh and another bank to access in the same cycle. Four bank interleaving is better than two bank. Most RAM chips 64 MB and over have 4 banks of chips.

Disabled: SDRAM bank interleaving is disabled. 16 MB SDRAM chips may only work with this option.
2 Bank: If using a two bank SDRAM chip. This option can be enabled for four bank chips but is not as fast.
4 bank: Set the field to this option if the system uses four bank chips or 2 two bank chips. 

DRAM Timing

This field determines the speed of the system SDRAM module. The option must match the speed of the SDRAM fitted. Some motherboards show fields for each bank separate and can use different speed or type of RAM. On newer motherboards the speed applies overall banks.

Fast: Set this option for SDRAM of PC100 specification. DRAM of 10 ns.
Normal: Set this option for PC133 SDRAM. DRAM of 8 ns.

SDRAM CAS Latency / SDRAM Cycle Length

This controls the time delay in clock cycles (CLKs) that passes before the SDRAM starts to carry out a read after receiving the command. This also determines the number of CLKs for the completion of the first part of a burst transfer. The lower the latency, the faster the transaction. 

2: for optimal performance if possible
3: if the system becomes unstable.

SDRAM RAS To CAS Delay

This field option sets the delay between the RAS (Row Address Strobe) and CAS (Column Address Strobe) signals. This occurs when the SDRAM is written to, read from or refreshed. 

2: Better performance but may result in unstability
3: Slower and more stable.

SDRAM Cycle Time

This field option, sets the minimum number of clock cycles required for the Tras and the Trc of the SDRAM. Tras refers to the SDRAM's Row Active Time, which is the length of time in which the row is open for data transfers. It is also known as Minimum RAS Pulse Width. Trc, on the other hand, refers to the SDRAM's Row Cycle Time, which determines the length of time for the entire row-open, row-refresh cycle to complete.

6/8: Slower and more stable
5/6: Cycles the SDRAM faster but the system may become unstable.

SDRAM RAS Precharge

This field option sets the number of cycles required for the RAS to accumulate its charge before the SDRAM refreshes. Reducing the precharge time improves SDRAM performance but if the precharge time is insufficient, the SDRAM may not be refreshed properly and it may fail to retain data.

2: Faster SDRAM performance, but may be unreliable
3: Reduces SDRAM performance, more reliable.

SDRAM Leadoff Command

This field sets the option to adjust the leadoff time needed before the data stored in the SDRAM can be accessed. In most cases, it is the access time for the first data element in a burst.

3: Faster SDRAM access times
4: The SDRAM performance is reduced but more reliable.

SDRAM Precharge Control

This field stes the option to determine if the processor or the SDRAM itself controls the precharging of the SDRAM. If this option is disabled, all CPU cycles to the SDRAM will result in an All Banks Precharge Command on the SDRAM interface which improves stability but reduces performance. If this feature is enabled, precharging is left to the SDRAM itself. This reduces the number of times the SDRAM is precharged since multiple CPU cycles to the SDRAM can occur before the SDRAM needs to be refreshed. So, enable it for optimal performance unless facing system stability issues with this option enabled.

disabled: Slower performance, improved stabilty
enabled: faster SDRAM performance. but may cause instability.

DRAM Data Integrity Mode / Memory Parity / ECC Checking

This field option  is used to configure the RAM's data integrity mode. ECC stands for Error Checking and Correction and should be used only if 72-bit ECC RAM is installed. This will enable the system to detect and correct single-bit errors. It will also detect double-bit errors though it will not correct them. This provides increased data integrity and system stability at the expense of a little speed.

ECC: If the system uses ECC RAM.
Non ECC: If the RAM is not ECC.

Read Around Write

This BIOS feature allows the processor to execute read commands out of order, as if they are independent from the write commands. So, if a read command points to a memory address whose latest write (content) is in the cache (waiting to be copied into memory), the read command will be satisfied by the cache contents instead, and so would not have to read the content from RAM and would speed up the memory subsystem.

enabled: faster execution if the data is in the cache
disabled: slower execution if data is in the cache.

System BIOS Cacheable

This field enables or disables the caching of the system BIOS ROM at address F0000h to FFFFFh via the secondary cache (L2). This speeds up accesses to the system BIOS. However, the Windows OS does not need to access the system BIOS much. It would be a waste of secondary cache usage to cache the system BIOS instead of system data. If any program writes into this memory area, it will result in a system crash.

Enabled: Enables caching of the system BIOS ROM. Use with a DOS only system
Disabled: Disables caching of the system BIOS ROM. Optimal performance on non DOS system.

Video Bios Cacheable

This field enables or disables the caching of the video BIOS ROM at address C0000h to C7FFFh via the L2 cache. This can speed up accesses to the video BIOS. Because Windows OS (but not DOS) bypasses the BIOS using the graphics driver to access the video card's hardware directly this may not give better performance.

Enabled: Enables caching of the video BIOS ROM. Use with a DOS only system
Disabled: Disables caching of the video BIOS ROM. Optimal performance on non DOS systems.

Video Ram Cacheable

This field enables or disables the caching of the video RAM at address A0000h to AFFFFh via the L2 cache. This is supposed to speed up accesses to the video RAM, but many graphics cards have a RAM bandwidth far higher than secondary cache.

Enabled: May be useful in speeding up older graphics cards on some DOS only systems
disabled: set this option for optimum performance on most systems.

Memory Hole At 15M-16M

Some special ISA cards require this area of memory for them to work properly. Enabling this function reserves the memory area for the card's use. It will also prevent the system from accessing memory above 16MB. If this option is enabled, the OS can only use up to 15MB of RAM, irrespective of how much RAM the system actually has. So, always disable this function unless the ISA card this memory area to work properly.

Enabled: OS reserves RAM over 15M for graphics card
Disabled: The OS does not reserve RAM for the graphics card above 15M.

8 Bit I/O Recovery Time

NA: For optimal ISA bus performance. 
Increase the I/O Recovery Time if there are problems with 8-bit ISA cards. Note that this function has no meaning if there are no ISA cards.

16 Bit I/O Recovery Time

NA: For optimal ISA bus performance. 
Increase the I/O Recovery Time if there are problems with 16-bit ISA cards. Note that this function has no meaning if there are no ISA cards.

Passive Release

Enabling this option sets CPU-to-PCI bus access during passive release of the PCI bus. The processor can access the PCI bus while the ISA bus is being accessed. Otherwise, the arbiter only accepts another PCI master access to local DRAM. Only another PCI bus master can access the PCI bus, not the processor. This function is used to meet the latency of the ISA bus master, which is much longer than that of the PCI bus master.

Enabled: For optimal performance.
Disabled: If there are problems with ISA cards.

Delay Transaction / PCI 2.1 Compliance

This field is used to enable the latency of PCI cycles to and from the ISA bus. The PCI cycles to and from the ISA bus take a longer time to complete and this slows the PCI bus down. Enabling Delayed Transaction enables the chipset's embedded 32-bit posted write buffer to support delayed transaction cycles. This means that transactions to and from the ISA bus are buffered and the PCI bus can be freed to perform other transactions while the ISA transaction is underway.

Enabled: Better performance and meet PCI 2.1 specifications.
Disabled: Set if PCI cards cannot work properly or if an ISA card is not PCI 2.1 compliant.

AGP Aperture Size

This field has options to select the size of the AGP aperture. The aperture is a portion of the PCI memory address range dedicated as graphics memory address space. Host cycles that hit the aperture range are forwarded to the AGP without need for translation. This size also determines the maximum amount of system RAM that can be allocated to the graphics card for texture storage. AGP Aperture size is set by the formula : maximum usable AGP memory size x 2 plus 12MB. That means that usable AGP memory size is less than half of the AGP aperture size. That's because the system needs AGP memory (uncached) plus an equal amount of write combined memory area and an additional 12MB for virtual addressing. This is address space, not physical memory used. The physical memory is allocated and released as needed only when Direct3D makes a "create non-local surface" call.
Win95 (with VGARTD.VXD) and Win98 use a "waterfall effect". Surfaces are created first in local memory. When that memory is full, surface creation spills over into AGP memory and then system memory. So, memory usage is automatically optimized for each application. AGP and system memory are not used unless absolutely necessary.
The size of the aperture does not correspond to performance so increasing it will not improve performance. Many graphics card, however, will require a larger than 8MB AGP aperture size to work properly so use a minimum value of 16MB for the AGP aperture size. As the amount of onboard RAM increases and texture compression becomes commonplace, there's less of a need for the AGP aperture size to increase beyond 64MB.

64MB: Use this setting most of the time
All other values: Appear to have no real effect.

AGP 2X Mode

This field enables or disables the AGP2X transfer protocol. The standard AGP1X only makes use of the rising edge of the AGP signal for data transfer. At 66MHz, this translates into a bandwidth of 264MB/s. AGP 2X Mode doubles that bandwidth by transferring data on both the rising and falling edges of the signal. While the clock speed of the AGP bus still remains as 66MHz, the effective bandwidth of the bus is doubled.

Enabled: AGP 2X Mode doubles the bandwidth, for a higher AGP transfer rate
Disabled: Standard AGP1X mode only, more stability.

Both the motherboard chipset and the graphics card must support AGP2X transfers before using the AGP2X transfer protocol. 

AGP Master 1WS Read

This BIOS option enables or disables the delay the AGP busmastering device waits before it starts a read transaction.

Enabled: For better AGP read performance
Disabled: if experiencing weird graphical anomalies like wireframe effects and pixel artifacts.

AGP Master 1WS Write

This BIOS option enables or disables the delay the AGP busmastering device waits before it starts a write transaction.

Enabled: For better AGP read performance
Disabled: if experiencing weird graphical anomalies like wireframe effects and pixel artifacts.

USWC Write Posting

USWC or Uncacheable Speculative Write Combination improves performance for Pentium Pro systems with graphic cards that have a linear framebuffer (all ours do). By combining smaller data writes into 64-bit writes, it reduces the number of transactions required for a particular amount of data to be transferred into the linear framebuffer of the graphics card.

Enabled: For faster graphics performance on Pentium Pro processors or motherboards based on older chipsets
Disabled: Improves reliability, slower performance.

Spread Spectrum / Auto Detect Dimm/PCI Clk

This field sets the option for reducing the EMI effect. When the motherboard's clock generator pulses, the extreme values (spikes) of the pulses creates EMI (Electromagnetic Interference). This function reduces the EMI generated by modulating the pulses so that the spikes of the pulses are reduced to flatter curves. It does so by varying the frequency so that it doesn't use any particular frequency for more than a moment. This reduces interference problems with other electronics in the area. System stability and performance may be slightly compromised with timing-critical devices like SCSI devices.

Enabled: Reduces system stability
Disabled: Optimal system stability and performance
 0.25%: Better system stability
 0.5%: Better for EMI reduction
Smart Clock: Turns off the AGP, PCI and SDRAM clock signals when not in use.

Flash BIOS Protection

This field sets a option to protect the BIOS from accidental corruption by unauthorized users or computer viruses.  To successfully update the BIOS, disable the Flash BIOS Protection function.

Enabled: Set to this option to prevent the BIOS data being changed
Disabled: Only needed when updating the BIOS.

DRAM Read Latch Delay

This is a BIOS option that introduces a small delay before the system reads data from a DRAM module to facilitate the use of some RAM that has unusual timings.

Enabled: For faster DRAM operation
Disabled: Set to increase system memory stability 

DRAM Interleave Time

This BIOS option controls the timing for reading the next bank of data when interleave enabled. Naturally, the lower the time used, the faster the DRAM modules can interleave and consequently, the better the performance.

0ms: Faster interleave and better performance
1ms: Slower performance but better reliability/

Byte Merge / Data Merge

This options enables or disables 8-bit or 16-bit writes from the CPU to the PCI bus to be held in a buffer and accumulated and merged into 32-bit writes. The chipset then writes the data in the buffer to the PCI bus when it can.

Enabled: Better PCI performance, reduces the number of PCI transactions
Disabled: Reduced PCI performance.

PCI Pipeline / PCI Pipelining

This field controls the byte-merge feature for frame-buffer cycles. The BIOS combines PCI or CPU pipelining with byte merging. Byte merging is then used to enhance performance of the graphics card.

Enabled: For better performance with a PCI graphics card
Disabled: No PCI Pipelining, more reliability.

AT Bus Clock

This field sets the speed of the AT bus. The value achieved is a division of the system bus and should be set to around 11 Mhz for optimum performance and reliability.

2/3: Divides the clock speed by 2 then by one third.
2/4: Divides clock speed by two then one quarter. Use with 100 Mhz Bus.

CPU/PCI Clock Select

This setting is dependent on the bus speed of the CPU installed. Normally the value what match the CPU, but by changing this to a higher bus speed it is possible to run the processor at a higher speed. For maximum system stability use the setting that matches the installed CPU.

Default: 100/33 MHz
66/33 MHz: For CPU using a 66MHz bus.
133/44 MHz: For this setting to work the PCI devices in the system must be able to support the higher speed. Also the speed of the AT bus and memory timing may be affected by this setting on some motherboards.

CPU Warning Temperature

This field is used to set the system/CPU warning temperature. The system sounds an audible alarm through the speaker inside the case. This option is useful on CPUs supporting thermal management and can prevent a processor from becoming useless by prompting early action. With the use of some IC monitoring software it is possible to reduce the power consumption of the CPU until a safe teperature has been reached.
Other alarms may be available for the Case and CPU fans, various system voltages such as core VTT, and general readings from the hardware monitoring IC.

xx-yy: Sounds an audible alarm if the system/CPU reaches this temperature.
Disabled: No monitoring of the system/CPU temperature by the BIOS.

Sustained 3T write

This field allows support for PBSRAM sustained 3T write.

Enabled: 
Disabled: 

ISA Line Buffer

This field Enables or disables the ISA line buffer.

Enabled: 
Disabled: 

Cache Rd + CPU Wt Pipeline

When enabled this option allows pipelining of cached reads and CPU writes. Enabling this option will enhance system performance.

Enabled: 
Disabled: 

Concurrent PCI/Host

When disabled the PCI bus will be occupied during the entire PCI operation period.

Enabled: 
Disabled: 

Primary Frame Buffer

This field sets the size of the frame buffer used when PCI Pipelining is enabled.

Enabled: 
Disabled: 

DRAM Read Pipeline

This option enables pipelining of DRAM reads. And can enhance the performance of the system.

Enabled: Enhances system performance.
Disabled: Reduces system performance, better stability.

VGA Frame Buffer

This option enables or disables the VGA frame buffer.

Enabled: 
Disabled: 

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Copyright © 2000 TotalSupport Computer Workshop
Last modified: December 15, 2000